1. Field of the Invention
The present invention generally relates to a semiconductor storage device having a divided word line structure and, more particularly, to a semiconductor storage device having a divided word line structure suitable for preventing the influence of noise generated among a plurality of adjacent sub-word lines.
2. Description of the Background Art
A divided word line (DWL) structure has been known as one type of structures of semiconductor storage devices. A semiconductor storage device of this type will be hereinafter referred to as a "DWL storage device."
FIG. 7 is a circuit diagram showing the principal elements of a former DWL storage device. A memory bank region 10 shown in FIG. 7 is a part of one of the plurality of memory banks possessed by the former DWL storage device. A plurality of memory cells (not shown) are two-dimensionally arranged in the memory bank region 10.
The former DWL storage device has a plurality of main word lines (MWL) including MWL&lt;0&gt; and MWL&lt;1&gt; shown in FIG. 7. MWL&lt;0&gt; and MWL&lt;1&gt; are provided so as to extend and pass through the memory bank region 10, being made of an aluminum wiring layer laid on the memory cells.
The former DWL storage device has a plurality of sub-word lines (SWL) including SWL&lt;0&gt; to SWL&lt;7&gt; shown in FIG. 7. SWL&lt;0&gt; to SWL&lt;7&gt; are transfer gates formed below MWL&lt;0&gt; and MWL&lt;1&gt;, being made from polysilicon. SWL&lt;0&gt; to SWL&lt;3&gt; pertain to one SWL group and are provided so as to correspond to MWL&lt;0&gt;. On the other hand, SWL&lt;4&gt; to SWL&lt;7&gt; pertain to another SWL group and are provided so as to correspond to MWL&lt;1&gt;. The group of SWL&lt;0&gt; to SWL&lt;3&gt; and the group of SWL&lt;4&gt; to SWL&lt;7&gt; are referred to as "the same group SWLs" hereunder.
Individual memory cells provided in the memory bank region 10 can be specified by designation of row and column addresses. In the former DWL storage device, MWL&lt;0&gt;, MWL&lt;1&gt;, and SWL&lt;0&gt; to SWL&lt;7&gt; are used for specifying the row address of the memory cell.
Further, the former DWL semiconductor storage device has a plurality of sub-decoder bands so that either side of each of the memory banks are provided with a sub-decoder band. Sub-decoder bands 12 and 14 shown in FIG. 7 are the ones which are placed on respective sides of the memory bank region 10.
In the sub-decoder band 12, there are provided a pair of sub-decode line SDL&lt;0&gt; and reverse sub-decode line /SDL&lt;0&gt;, and a pair of sub-decode line SDL&lt;2&gt; and reverse sub-decode line /SDL&lt;2&gt;. SDL&lt;0&gt; and SDL&lt;2&gt; are furnished with sub-decode signals SD&lt;0&gt; and SD&lt;2&gt; transmitted from an unillustrated sub-row decoder. Further, /SDL&lt;0&gt; and /SDL&lt;2&gt; are furnished with reverse signals /SD&lt;0&gt; and /SD&lt;2&gt; transmitted from an unillustrated sub-row decoder.
In the sub-decoder band 14, there are provided a pair of sub-decode line SDL&lt;1&gt; and reverse sub-decode line /SDL&lt;1&gt;, and a pair of sub-decode line SDL&lt;3&gt; and reverse sub-decode line /SDL&lt;3&gt;. SDL&lt;1&gt; and SDL&lt;3&gt; are furnished with sub-decode signals SD&lt;1&gt; and SD&lt;3&gt; transmitted from an unillustrated sub-row decoder. Further, /SDL&lt;1&gt; and /SDL&lt;3&gt; are furnished with reverse signals /SD&lt;1&gt; and /SD&lt;3&gt; transmitted from an unillustrated sub-row decoder.
SWL&lt;0&gt;, SWL&lt;2&gt;, SWL&lt;4&gt;, and SWL&lt;6&gt; are provided so as to pass through the sub-decoder band 12 and become open-ended in the vicinity of the sub-decoder band 14. These sub-word lines will be hereinafter referred to as "even-numbered sub-word lines." In contrast, SWL&lt;1&gt;, SWL&lt;3&gt;, SWL&lt;5&gt;, and SWL&lt;7&gt; are provided so as to pass through the sub-decoder band 14 and become open-ended in the vicinity of the sub-decoder band 12. These sub-word lines will be hereinafter referred to as "odd-numbered sub-word lines."
SWL&lt;0&gt; is connected to an even-numbered common ground line 18 by way of an N-type MOS transistor 16, as well as to the even-numbered common ground line 18 and SDL&lt;0&gt; by way of a transistor pair 20. The gate of the N-type MOS transistor 16 is connected to /SDL&lt;0&gt;. The transistor pair 20 comprises an N-type MOS transistor 22 and a P-type MOS transistor 24. MWL&lt;0&gt; is connected to the gate of the N-type MOS transistor 22 and to the gate of the P-type MOS transistor 24.
As in the case of SWL&lt;0&gt;, the even-numbered sub-word line SWL&lt;2&gt; is connected to the even-numbered common ground line 18 and MWL&lt;0&gt; by way of the N-type MOS transistor 16 and the transistor pair 20, and the even-numbered sub-word lines SWL&lt;4&gt; and SWL&lt;6&gt; are connected to the even-numbered common ground line 18 and MWL&lt;1&gt; by way of the N-type MOS transistor 16 and the transistor pair 20. On the other hand, the odd-numbered sub-word lines SWL&lt;1&gt; and SWL&lt;3&gt; are connected to the odd-numbered common ground line 26 and MWL&lt;0&gt; by way of the N-type MOS transistor 16 and the transistor pair 20, and the odd-numbered sub-word lines SWL&lt;5&gt; and SWL&lt;7&gt; are connected to the odd-numbered common ground 26 and MWL&lt;1&gt; by way of the N-type MOS transistor 16 and the transistor pair 20.
In the former DWL storage device, an unillustrated main-row decoder is connected to MWL&lt;0&gt; and MWL&lt;1&gt;. When a designated main row address corresponds to any of SWL&lt;0&gt; to SWL&lt;3&gt;, the main row decoder supplies a boost potential Vpp to MWL&lt;0&gt;. In contrast, when the designated row address does not correspond to any one of SWL&lt;0&gt; to SWL&lt;3&gt;, the main row decoder maintains MWL&lt;0&gt; at a ground potential GND. Similarly, when the designated row address corresponds to any of SWL&lt;4&gt; to SWL&lt;7&gt;, the main row decoder supplies the boost potential Vpp to MWL&lt;1&gt;. In contrast, when the designated row address does not correspond to any one of SWL&lt;4&gt; to SWL&lt;7&gt;, the main row decoder maintains MWL&lt;1&gt; at the ground potential Vss.
In the former DWL storage device, when the designated row address corresponds to the sub-word line which is belongs to the even-numbered sub-word line and is assigned the lowest reference numeral among the same group SWLs; more specifically, the designated row address corresponding to SWL&lt;0&gt; or SWL&lt;4&gt;, the foregoing sub-row decoder brings SD&lt;0&gt; to the boost potential Vpp and brings /SD&lt;0&gt; into the ground potential Vss. At this time, the remaining sub-decode signals SD&lt;1&gt; to SD&lt;3&gt; are maintained at the ground potential Vss, and the remaining reverse sub-decode signals /SD&lt;1&gt; to /SD&lt;3&gt; are maintained at the boost voltage Vpp.
When the designated row address corresponds to SWL&lt;2&gt; or SWL&lt;6&gt;, the sub-row decoder brings SD&lt;2&gt; to the boost potential Vpp and brings /SD&lt;2&gt; to the ground potential Vss. Likewise, when the designated row address corresponds to SWL&lt;1&gt; or SWL&lt;5&gt; the sub-row decoder brings the sub-decode signal corresponding to the designated sub-word line (i.e., SD&lt;1&gt;) to the boost voltage Vpp and brings the reverse signal corresponding to the designated sub-word line (i.e., /SD&lt;1&gt;) to the ground potential Vss. Similarly, when the designated row address corresponds to SWL&lt;3&gt; or SWL&lt;7&gt;, the sub-row decoder brings the sub-decode signal corresponding to the designated sub-word line (i.e., SD&lt;3&gt;) to the boost voltage Vpp and brings the reverse signal corresponding to the designated sub-word line (i.e., /SD&lt;3&gt;) to the ground potential Vss.
In the former DWL storage device, when the row address corresponding to SWL&lt;0&gt; is designated, MWL&lt;0&gt; is brought to the ground potential Vss. As a result, the P-type MOS transistor of the transistor pair 20 is turned on, and SWL&lt;0&gt; and SDL&lt;0&gt; are brought into conduction. Further, SD&lt;0&gt; is brought into the boost potential Vpp, and /SD&lt;0&gt; is brought into the ground potential Vss under the foregoing designation. In this case, the boost potential Vpp is transmitted to SWL&lt;0&gt; from SDL&lt;0&gt; while the N-type MOS transistor 16 is turned off. As a result, SWL&lt;0&gt; is brought into a high potential.
When the row address corresponding to SWL&lt;0&gt; is designated, SWL&lt;1&gt; and SWL&lt;3&gt; are each connected to the common ground line 26 by way of the N-type MOS transistors 16, and SWL&lt;2&gt; is connected to the common ground line 18 by way of the N-type MOS transistor 16. Further, SWL&lt;1&gt; to SWL&lt;3&gt; are connected to SDL&lt;1&gt;, SDL&lt;2&gt;, or SDL&lt;3&gt;, respectively by way of the transistor pairs 20. At this time, SDL&lt;1&gt; to SDL&lt;3&gt; are receiving the ground potential Vss. Accordingly, SWL&lt;1&gt; to SWL&lt;3&gt; are maintained at the ground potential Vss.
When the row address corresponding to SWL&lt;0&gt; is designated as mentioned above, SWL&lt;4&gt; is connected to the common ground line 18 by way of the transistor pair 20. Further, in this case, SWL&lt;5&gt; and SWL&lt;7&gt; are each connected to the common ground line 26 by way of the N-type MOS transistor 16 and the transistor pair 20, and SWL&lt;6&gt; is connected to the common ground line 18 by way of the N-type MOS transistor 16 and the transistor pair 20. Accordingly, SWL&lt;5&gt; to SWL&lt;7&gt; are maintained at the ground potential Vss. As mentioned above, the former DWL storage device enables selective activation of only the sub-word line corresponding to the designated address.
In the storage device, the word line which permits transmission of a signal corresponding to a row address is formed primarily for the purpose of reduction of resistance by combination of a metal wiring pattern and a transfer gate (i.e., a polysilicon wiring pattern). To realize such a configuration of the word line, the metal wiring pattern must be formed above the memory cells, i.e., above an irregular surface including convex portions and concave portions which stem from the memory cells, as in the case of the foregoing main word line. For this reason, ensuring dimensional accuracy of the metal wiring pattern is more difficult than ensuring that of the transfer gate.
In the former DWL storage device, the word line is formed by combination of a main word line (a metal wiring pattern) and sub-word lines (transfer gates), and the main word line is provided so as to be shared among a plurality of sub-word lines. With such a configuration, even if a large tolerance in dimensional accuracy of the main word line is allowed, there can be ensured stable-yield manufacture of a semiconductor storage device. Accordingly, according to the former DWL storage device, there can be ensured stable-yield manufacture of a higher-integration semiconductor storage device having higher-density word lines.
However, in the former DWL storage device, the sub-word lines (including SWL&lt;0&gt; to SWL&lt;7&gt;) receive the boost voltage Vpp or the ground voltage Vss at one end of the memory bank, and being open-ended at the other end of the memory bank. Further, the even-numbered sub-word lines, which are open-ended at one end of the memory bank, and the odd-numbered sub-word lines, which are open-ended at the other end of the memory bank are alternately disposed in order to efficiently provide the N-type MOS transistor 16 and the transistor pair 20 in the sub-decoder regions (including the sub-decoder bands 12 and 14).
With the foregoing structure, as indicated by A part and B part in FIG. 7, the open ends of some sub-word lines locates near voltage-receiving ends of other sub-word lines. When the sub-word line receives the boost voltage Vpp, the voltage-receiving end has the highest voltage among all portions of the sub-word line. On the other hand, when the sub-word line is grounded, the open end is the most susceptible to noise among all portions of the sub-word line.
For these reasons, since the open ends of the sub-word lines are coupled with the voltage-receiving ends of the adjacent sub-word lines, the open ends of the sub-word lines are susceptible to superimposition of noise. When noise is superimposed on the open end of an inactivated sub-word line as a result of activation of other certain sub-word line, data stored in the memory cell corresponding to the inactivated sub-word line may be corrupted.
Further, the former DWL storage device allows the even-numbered sub-word lines SWL&lt;0&gt;, SWL&lt;2&gt;, SWL&lt;4&gt;, and SWL&lt;6&gt; to be brought into conduction with the common ground line 18 simultaneously while all of those lines are inactive. Similarly, the odd-numbered sub-word lines SWL&lt;1&gt;, SWL&lt;3&gt;, SWL&lt;5&gt;, and SWL&lt;7&gt; may be brought into conduction with the common ground line 26 while all of those lines are inactive.
When a certain sub-word line is changed between an active state and an inactive state, the sub-word line becomes recharged or discharged. When the sub-word line becomes recharged or discharged, noise is superimposed on the common ground line 18 or 26 connected to the sub-word line. The thus-superimposed noise is then transmitted to other sub-word lines connected to the common ground line 18 or 26. At this time, if the noise superimposed on the sub-word line exceeds the threshold voltage of the memory cell corresponding to the sub-word line, the data stored in the memory cell may be corrupted.
As mentioned previously, the former DWL storage device has the advantage of ensuring high-yield manufacture of a storage device under requirements for high-density circuitry. In contrast, the former device has a disadvantage of readily corrupting data of non-designated memory cells when a certain sub-word line is brought into an active state following a designation of a row address, or when the sub-word line is brought into an inactive state.